The present invention relates to the enlargement of a noise margin of a semiconductor logic circuit (LSI), or more particularly to a dynamic logic circuit suitable for large-scale integration with a soft error margin enlarged against .alpha. rays without sacrificing the high-speed operation characteristics of CMOS and BiCMOS logic circuits in the LSI.
A high-speed logic circuit for MOS LSI comprising a logic section configured of MOS FETs for effecting a predetermined logic operation by dynamic action and a CMOS or BiCMOS output buffer for outputting the result of the logic operation is well known, as disclosed in JP-A-54-89558, JP-A-62-98827 and JP-A-59-2438.
Generally, the operation of a dynamic logic circuit includes a precharging operation for making preparations before performing logic operation and a subsequent operation. These operations are performed in the manner mentioned below in a conventional system shown in FIG. 1A. (Reference is made, for example, to SESSION IV: HIGH-SPEED CIRCUIT TECHNOLOGY WAM 4,6: "TWO (MOS 0.5 .mu.m 326 Digital Macros" by Chih-Liang Chen et al. IBM Research Center pp. 62-63, 1987 IEEE ISCC, or U.S. patent application Ser. No. 07/246,196, entitled "Semiconductor Logic circuit" filed on Sept. 19, 1988 and assigned to the same assignee as the present invention.)
First, for performing the precharging operation, a clock signal input terminal 51 is set to the ground potential (hereinafter assumed to be "low level"). As a result, a PMOS FET 1 is turned on and NMOS FET 19 off. In the meantime, input signals A to E are set to low level by a circuit not shown in the diagram. An output node of a logic section 61 (dynamic node) 41 is charged to a source potential (hereinafter referred to as "high level") by the PMOS FET 1, so that a PMOS FET 6 turns off and an NMOS FET 7 turns on, thus reducing the output terminal 43 to low level.
Now, the logic operation will be explained. When the clock signal input terminal 51 is set to high level, the PMOS FET 1 turns off and the NMOS FET 19 turns on. If current conduction takes place between the logic section output node 41 and the grounded terminal by data inputs to the input terminals A to E, electric charges stored at the node 41 by the precharging operation are discharged to the ground, and the potential of the same node drops, whereupon the PMOS FET 6 turns on and the NMOS FET 7 turns off. Thus a parasitic capacitor 102 is charged through the PMOS FET 6, and the output terminal 43 increases to high level, thus completing the logic operation.
The charges stored at the logic section output node 41 are charged also to a parasitic capacitance 101 mainly including a wiring capacitance and a gate capacitance of the PMOS FET 6 and the NMOS FET 7. Through study of these circuits, the attention of the present inventors was drawn to facts mentioned below.
The quantity of noise charges due to alpha (.alpha.) rays has not posed a problem in the past in comparison it is small as with the quantity of charges stored at the parasitic capacitance. With the reduction in size of integration circuits and the resulting decrease in the capacitance thereof, however, the quantity of the charges stored in the capacitance has also decreased, thereby making it difficult to ignore the quantity of noise charges due to alpha rays. The problem has thus come up in which the logic is reversed by noise charge when alpha ray is bombarded on a transistor. This problem becomes more important with the decrease in source voltage which decreases the quantity of charges to the capacitance.
Another conventional circuit is shown in FIG. 2. This circuit has a PMOS FET 50 (feedback PMOS) add to the conventional circuit of FIG. 1A. In the circuit of FIG. 2, the problem of charge share may be solved by increasing the gate width of the PMOS FET 50, but the rate of delay in logic operations increases rapidly with the increase in the gate width of the PMOS FET 50. Specifically, as taken up at the 1987 Symposium on VLSI Circuits, Karuizawa, (High-Speed on VLSI Circuit for Mainframe VLSI, p. 93 to 94) which dealt with the use of the circuit shown in FIG. 2 for solving the problem of charge share, the increase in the gate width of the PMOS FET 50 gives rise to the problem of rapidly increasing the rate of computation delay. The above cited paper deals only with a measure against such a charge share problem and does not recognize or offer any solution to the soft error problem caused by x particles.